1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a capacitor protection layer and a method of manufacturing the same.
2. Description of the Related Art
Recently, in the field of a semiconductor memory device manufacture, great interest has been focused on a method of forming a capacitor dielectric layer with a ferroelectric material. This is because in non-volatile semiconductor devices, remnant polarization (Pr) of the ferroelectric material is compatible with the concept of a binary memory which forms the basis of digital memory devices which have been widely used. At present, there are two main ferroelectric materials in use: PZT (Pb(Zr, Ti)O3 and SBT(SrBi2Ta2O9).
However, in forming a capacitor dielectric layer of a semiconductor memory device with a ferroelectric material, a serious problem is the deterioration in ferroelectric characteristics of the ferroelectric material during the integration processes of a semiconductor memory device carried out after the formation of a capacitor. In more detail, the formation of a capacitor is followed by an interlayer dielectric (ILD) process, an intermetal dielectric (IMD) process, a passivation process and the like. During these processes, contaminants, particularly, hydrogen ions, are derived. The derived hydrogen ions may directly diffuse into the capacitor, or may gradually diffuse into the capacitor, after being incorporated into an ILD layer, an IMD layer or a passivation layer during the formation processes thereof. As a result, the residual polarization (Pr), (one of the ferroelectric characteristics of the ferroelectric material used as a capacitor dielectric layer), decreases below a critical level, so that a capacitor may malfunction.
For example, when a ferroelectric capacitor formed on a semiconductor, is exposed during the ILD process to form an ILD film of a silicon oxide layer thereon, the capacitor dielectric layer is deteriorated. That is, in the ILD process for forming an ILD layer with a silicon oxide layer using plasma enhanced chemical vapor deposition (PECVD), silane gas (SiH4) and oxygen gas (O2) are used as reaction gases, and hydrogen ions are derived as a byproduct. The derived hydrogen ions directly diffuse into the dielectric layer of the ferroelectric capacitor or are incorporated into an ILD film formed in the ILD process, thereby deteriorating the capacitor dielectric layer. As a result, the Pr value of the capacitor dielectric layer is lowered to a critical level, causing a degradation of the ferroelectric characteristics of the capacitor dielectric layer. The deterioration of the capacitor dielectric layer in the integration procedure of a semiconductor memory device is not limited to the ILD process only, but occurs in the IMD process for forming an IMD film as well as the passivation process for forming an passivation layer.
To solve this problem, a conventional semiconductor memory device manufacturing technique has adopted a method of encapsulating a capacitor with a single insulating layer. For example, U.S. Pat. No. 5,822,175 teaches a method of encapsulating a capacitor with a silicon oxide layer, a doped silicon oxide layer or a silicon nitride layer for the purpose of preventing deterioration of a capacitor dielectric layer by diffusion of hydrogen.
Meanwhile, in the formation of a capacitor, after a capacitor dielectric layer is formed on a semiconductor substrate, it is heated to be crystallized at a temperature of 600 to 800xc2x0 C. in an oxygen atmosphere, so that its insulating characteristics can be enhanced. In addition, after the capacitor is formed, a heat treatment is performed at a temperature of 450 to 600xc2x0 C. in an oxygen atmosphere, so as to repair damage caused in the dry etching step performed during the formation of the capacitor, and stabilize the obtained capacitor.
However, during the heat treatment, oxygen diffuses into a contact plug which electrically connects a impurity-doped region, for example, source region and the capacitor, thereby increasing contact resistance. For example, in the case where the contact plug is formed of doped polysilicon, oxygen which diffuses into the contact plug reacts with the polysilicon, to thereby form a silicon oxide layer at the interface between the contact plug and the capacitor. As a result, a contact resistance is increased to the extent that the operating speed of a semiconductor memory device is slowed down.
To solve the above problems, it is an object of the present invention to provide a semiconductor memory device having a capacitor protection layer, which prevents deterioration of a capacitor dielectric layer by diffusion of contaminants, and a material layer for forming a low-resistance contact.
It is another object of the present invention to provide a method of manufacturing a semiconductor memory device, which ensures capacitor protection in semiconductor device integration performed after the formation of a capacitor.
To achieve the first object of the present invention, one embodiment of the semiconductor memory device according to the present invention comprises a capacitor having a lower electrode, an upper electrode and a capacitor dielectric layer interposed between the lower and upper electrodes. An encapsulating layer also is provided having a multi-layered structure. The encapsulating layer may cover the entire surface of the capacitor and comprising at least two material layers formed of different insulating materials. A dielectric layer also is formed on the encapsulating layer, and a metal contact is formed through the encapsulating layer and the dielectric layer to contact the upper electrode.
Preferably, the encapsulating layer comprises at least a blocking layer and a capacitor protection layer, the blocking layer being under the capacitor protection layer, and the blocking layer and the capacitor protection layer are formed of different material layers. If the encapsulating layer has a bilayered structure, the blocking layer may be a dielectric layer covering the entire surface of the capacitor, except for a portion of the upper electrode on which the metal contact is formed, and the capacitor protection layer may be a dielectric layer covering the entire surface of the blocking layer. Preferably, the blocking layer is formed of a material layer capable of preventing a reaction between a material layer, which is formed under the blocking layer, and the capacitor protection layer. More preferably, the blocking layer is formed of a TiO2 layer, a Ta2O5 layer, a BaTiO3 layer, a SrTiO3 layer, a Bi4Ti3O12 layer or a PbTiO3 layer.
Preferably, the capacitor protection layer is formed of a material layer capable of preventing diffusion of hydrogen entrapped in the dielectric layer formed on the capacitor protection layer into the capacitor dielectric layer, and more preferably, the capacitor protection layer is formed of an Al2O3 layer, a TiO2 layer, a Ta2O5 layer, a BaTiO3 layer, a SrTiO3 layer, a Bi4Ti3O12 layer or a PbTiO3 layer. Preferably, the material layer for the capacitor protection layer is different from the material layer for the blocking layer.
The semiconductor memory device may further comprise a passivation layer over the metal contact and the dielectric layer. In addition, a hydrogen barrier layer may be optionally interposed between the metal contact and the passivation layer so as to block diffusion of hydrogen (incorporated in the passivation layer 138) into the capacitor dielectric layer. Preferably, the hydrogen barrier layer is formed of an Al2O3 layer, a TiO2 layer, a Ta2O5 layer, a BaTiO3 layer, a SrTiO3 layer, a Bi4Ti3O12 layer or a PbTiO3 layer.
The semiconductor memory device according to the present invention may further comprise an interlayer dielectric film under the capacitor and a conductive plug formed through the interlayer dielectric film. The conductive plug may be electrically connected to the capacitor lower electrode and an interface layer formed of a cobalt silicide layer which extends between the capacitor lower electrode and the conductive plug.
The semiconductor memory device according to the present invention may further comprise an interlayer dielectric layer under the capacitor and a conductive plug formed through the interlayer dielectric film. The conductive plug may be electrically connected to the capacitor lower electrode. The conductive plug may be formed exclusively of a cobalt silicide layer or as a bilayer of a conductive layer and a cobalt silicide layer.
Another embodiment of the semiconductor memory device according to the present invention comprises a capacitor having a lower electrode, an upper electrode and a capacitor dielectric layer interposed between the lower and upper electrodes. An encapsulating layer also may be provided to cover the entire surface of the capacitor. The encapsulating layer may have a multi-layered structure at least including a blocking layer and a capacitor protection layer formed of different insulating materials, wherein the blocking layer is formed under the capacitor protection layer.
Still another embodiment of the semiconductor memory device according to the present invention comprises a capacitor having a lower electrode, an upper electrode and a capacitor dielectric layer interposed between the lower and upper electrodes. A dielectric layer is formed over the capacitor. A metal contact is formed through the dielectric layer to contact the upper electrode and a passivation layer is formed over the metal contact. In this embodiment, a hydrogen barrier layer is interposed between the metal contact and the passivation layer.
To achieve the second object of the present invention, one embodiment of the method for manufacturing a semiconductor memory device comprises the steps of forming a capacitor having a lower electrode, an upper electrode and a capacitor dielectric layer interposed between the lower and upper electrodes. An encapsulating layer also is formed with a multi-layered structure to thereby cover the entire surface of the capacitor.
The encapsulating layer with a multi-layered structure may include a blocking layer and a capacitor protection layer which are formed of different materials. The blocking layer may be formed under the capacitor protection layer. For a bilayered encapsulating layer, a blocking layer covers the entire surface of the capacitor, and in turn a capacitor protection layer covers the blocking layer.
In the semiconductor memory device manufacturing method according to the present invention, after the formation of the blocking layer, a heat treatment process may be performed at a temperature of approximately 400 to 600xc2x0 C. in an oxygen atmosphere. The blocking layer may be formed of a material capable of preventing a reaction between the underlying layer and the capacitor protection layer, and/or capable of preventing volatilization of the capacitor dielectric material. Preferably, the blocking layer may be a TiO2 layer, a Ta2O5 layer, a BaTiO3 layer, a SrTiO3 layer, a Bi4Ti3O12 layer or a PbTiO3 layer.
The capacitor protection layer may be formed of a material layer that is capable of blocking diffusion of hydrogen into the capacitor dielectric layer. Preferably, the capacitor protection layer may be formed of a TiO2 layer, a Ta2O5 layer, an Al2O3 layer, a BaTiO3 layer, a SrTiO3 layer, a Bi4Ti3O12 layer a PbTiO3 layer. Here, the capacitor protection layer is formed of a different material from the material used to form the blocking layer.
In the semiconductor memory device manufacturing method according to the present invention, after the formation of the encapsulating layer, the steps of forming a dielectric layer on the encapsulating layer, forming a metal contact through the dielectric layer to contact the upper electrode and forming a passivation layer over the semiconductor substrate having the metal contact, may be performed.
Prior to the formation of the passivation layer, a hydrogen barrier layer may be formed over the entire surface of the semiconductor substrate. Preferably, the hydrogen barrier layer may be formed of an Al2O3 layer, a TiO2 layer, a Ta2O5 layer, a BaTiO3 layer, a SrTiO3 layer, a Bi4Ti3O12 layer or a PbTiO3 layer. Preferably, the hydrogen barrier layer is formed by an atomic layer deposition (ALD) process.
In another embodiment of the semiconductor memory device manufacturing method according to the present invention, includes forming a predetermined semiconductor integrated circuit device on a semiconductor substrate and forming a passivation layer over the semiconductor substrate having the semiconductor integrated circuit device. A hydrogen barrier layer also may be formed over the entire surface of the semiconductor substrate prior to formation of the passivation layer.